Title :
A Chip-ID generating circuit for dependable LSI using random address errors on embedded SRAM and on-chip memory BIST
Author :
Fujiwara, H. ; Yabuuchi, M. ; Nakano, H. ; Kawai, H. ; Nii, K. ; Arimoto, K.
Author_Institution :
Renesas Electron. Corp., Tokyo, Japan
Abstract :
A chip-ID generating scheme with high-tamper resistance is proposed. This enables to extract a unique finger print from each chip by using random failure bits in an SRAM under the ID generation mode, and on-chip memory BIST. The stability and average of Humming distance of 128 bit ID become 99.9999999% and 63.9, respectively. The proposed scheme does not require any additional hardware IPs.
Keywords :
SRAM chips; built-in self test; embedded systems; large scale integration; Humming distance; chip-ID generating circuit; dependable LSI; embedded SRAM; finger print; on-chip memory BIST; random address errors; word length 128 bit; Built-in self-test; Circuit stability; Random access memory; Semiconductor device measurement; System-on-a-chip; Temperature sensors; Voltage control;
Conference_Titel :
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-61284-175-5
