Title :
An 8×10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects
Author :
Dickson, Timothy O. ; Liu, Yong ; Rylov, Sergey V. ; Dang, Bing ; Tsang, Cornelia K. ; Andry, Paul S. ; Bulzacchelli, John F. ; Ainspan, Herschel A. ; Gu, Xiaoxiong ; Turlapati, Lavanya ; Beakes, Michael P. ; Parker, Benjamin D. ; Knickerbocker, John U. ;
Author_Institution :
T.J. Watson Res. Center, IBM, Yorktown Heights, NY, USA
Abstract :
A serial I/O chip set in 45 nm SOI CMOS is mounted via 50 μm pitch micro-C4 bumps to a silicon carrier and communicates over ultra-dense interconnects with pitches of between 8 μm and 22 μm. With DFE-IIR RX equalization, data is received over distances up to 6 cm with channel losses as high as 16.3dB. The energy efficiency is better than 6.1pJ/bit.
Keywords :
CMOS integrated circuits; decision feedback equalisers; integrated circuit interconnections; microprocessor chips; silicon; silicon-on-insulator; DFE-IIR RX equalization; SOI CMOS; channel losses; energy efficiency; high-density silicon carrier interconnects; loss 16.3 dB; pitch micro-C4 bumps; serial I/O chip set; size 45 nm; size 50 mum; source-synchronous I/O system; ultra-dense interconnects; CMOS integrated circuits; Clocks; Data communication; Integrated circuit interconnections; Loss measurement; Silicon; Stripline;
Conference_Titel :
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-61284-175-5
