Title :
A 5.6Gb/s 2.4mW/Gb/s bidirectional link with 8ns power-on
Author :
Zerbe, Jared ; Daly, Barry ; Dettloff, Wayne ; Stone, Teva ; Stonecypher, William ; Venkatesan, Pravin ; Prabhu, Kashinath ; Su, Bruce ; Ren, Jihong ; Tsang, Brian ; Leibowitz, Brian ; Dunwell, Dustin ; Carusone, Anthony Chan ; Eble, John
Author_Institution :
Rambus Inc., Sunnyvale, CA, USA
Abstract :
A fast power-on low-power signaling system was developed and fabricated in TSMC´s 40nm LP process. The system uses matched source-synchronous clocking (MSSC), fast power-on bias, a rapid turn-on 4× multiplying ILO, and CML clock distribution to achieve 2.5-5.6Gb/s/lane and 8ns turn on at 2.4mW/Gb/s per link across a 6-lane parallel interface. First-edge clock jitter is minimized by using matching equalizers in the clock and data paths. PSN is reduced by using a staggered bias turn-on.
Keywords :
clocks; equalisers; jitter; power electronics; telecommunication links; CML clock distribution; bidirectional link; equalizer; first-edge clock jitter; low-power signaling system; matched source-synchronous clocking; parallel interface; power 2.4 mW; staggered bias turn-on; time 8 ns; Bandwidth; Bit error rate; Clocks; Delay; Jitter; Noise; Synchronization;
Conference_Titel :
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-61284-175-5
