Title :
A 2.8 mW ΔΣ ADC with 83 dB DR and 1.92 MHz BW using FIR outer feedback and TIA-based integrator
Author :
Gealow, Jeffrey ; Ashburn, Michael ; Lou, Chih-Hong ; Ho, Stacy ; Riehl, Patrick ; Shabra, Ayman ; Silva, José ; Yu, Qicheng
Author_Institution :
MediaTek Wireless Inc., Woburn, MA, USA
Abstract :
A low-power continuous-time ΔΣ ADC for HSDPA (High-Speed Downlink Packet Access) applications provides 83 dB dynamic range and 1.92 MHz bandwidth. A high sample rate (245.76 MHz) and an FIR filter in the outer feedback path minimize susceptibility to jitter. A TIA-based integrator with direct connection of inner feedback DAC current sources to integration capacitors supports the high sample rate. The modulator, implemented using 40 nm CMOS, dissipates only 2.8 mW and achieves a 110 fJ / conversion step figure-of-merit.
Keywords :
CMOS digital integrated circuits; FIR filters; analogue-digital conversion; delta-sigma modulation; modulators; packet radio networks; CMOS; FIR filter; FIR outer feedback; HSDPA; TIA-based integrator; continuous-time ΔΣ ADC; conversion step figure-of-merit; frequency 1.92 MHz; gain 83 dB; high-speed downlink packet access; inner feedback DAC current sources; low-power ΔΣ ADC; modulator; power 2.8 mW; size 40 nm; Bandwidth; Delay; Finite impulse response filter; Modulation; Noise; Resonator filters; Very large scale integration;
Conference_Titel :
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-61284-175-5
