Unified understanding of Vth and Id variability in tri-gate nanowire MOSFETs

We present the systematic study of V_th and I_dlin/I_dsat variability of nanowire transistors (NW Tr.) with various parameters (NW width (W_NW) and height (H_NW) down to 10nm, NW number (N_NW), NW directions, channel dopants). By adopting NW circumference as W_eff, the universal line appears in Pelgrom plot of both σV_th and σI_d for a wide range of gate length (L_g), W_NW and H_NW. We found A_vt reduction in NW Tr. compared to planar SOI Tr. due to gate grain alignment. Deviation of σV_th and σI_dlin of the narrowest Tr. from the universal line was eliminated by suppressing the parasitic resistance (R_SD). σI_dsat and σI_dlin in NW Tr. can be reduced by improving the surface-roughness-limited mobility and its variations, respectively.