Dual-loop system of distributed microregulators with high DC accuracy, load response time below 500ps, and 85mV dropout voltage

Author

Toprak-Deniz, Zeynep ; Bulzacchelli, John ; Rasmus, Todd ; Iadanza, Joseph ; Bucossi, William ; Kim, Seongwon ; Blanco, Rafael ; Cox, Carrie ; Chhabra, Mohak ; Leblanc, Christopher ; Trudeau, Christian ; Friedman, Daniel

Author_Institution

T.J. Watson Res. Center, IBM, Yorktown Heights, NY, USA

fYear

2011

fDate

15-17 June 2011

Firstpage

274

Lastpage

275

Abstract

A dual-loop architecture employs 8 distributed microregulators (UREGs) to achieve response times below 500ps in 45nm SOI CMOS. The trip point of an asynchronous comparator inside each UREG is tuned for high DC accuracy with a local charge pump, which receives UP/DOWN currents from a slow outer feedback loop. Measured DC load regulation is better than 10mV down to a dropout voltage of 85mV, and jitter readings in a CMOS delay line application indicate output noise below 28mVpp.

Keywords

CMOS integrated circuits; comparators (circuits); jitter; silicon-on-insulator; voltage regulators; CMOS delay line; DC accuracy; SOI; UREG; asynchronous comparator; distributed microregulators; dropout voltage; dual-loop architecture; dual-loop system; jitter; load response time; voltage 85 mV; CMOS integrated circuits; Calibration; Delay lines; Jitter; Regulators; Time factors; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2011 Symposium on

Conference_Location

Honolulu, HI

ISSN

2158-5601

Print_ISBN

978-1-61284-175-5

Type

conf

Filename

5986450