A stochastic network calculus based approach for on-chip networks

As the number of intellectual property (IP) cores in networks-on-chip (NoCs) continues to increase, the communication between IP cores presents nondeterministic characteristic. It is important to study the various stochastic factors that arise as the complexity of NoCs communication increases. In this paper, we address the issue of stochastic characteristics in an on-chip network with 2D tile-based mesh topology, based on which a generalized stochastically bounded bursty (gSBB) based traffic model is established. Within this model, the end-to-end performance is evaluated in terms of delay and backlog. Comparing with the results produced by cycle-accurate booksim-based simulator, we verify the effectiveness of our proposed model, which provides valuable guidelines for the early design of NoCs infrastructures.