• DocumentCode
    55117
  • Title

    Gate Voltage Matching Investigation for Low-Power Analog Applications

  • Author

    Joly, Y. ; Lopez, L. ; Truphemus, L. ; Portal, J. ; Aziza, H. ; Julien, F. ; Fornara, P. ; Masson, P. ; Ogier, J. ; Bert, Y.

  • Author_Institution
    STMicroelectron., Rousset, France
  • Volume
    60
  • Issue
    3
  • fYear
    2013
  • fDate
    Mar-13
  • Firstpage
    1263
  • Lastpage
    1267
  • Abstract
    On CMOS technology, some process steps can create a parasitic phenomenon named “hump effect.” This parasitic effect can have a strong impact on gate voltage matching of differential pairs and, as a consequence, on analog circuit performances. In this context, several solutions to limit or remove this hump effect are proposed and described. Silicon data obtained at package and wafer levels for different temperatures are analyzed.
  • Keywords
    CMOS analogue integrated circuits; elemental semiconductors; low-power electronics; silicon; CMOS technology; Si; analog circuit performances; gate voltage matching investigation; hump effect; low-power analog application; package level; parasitic effect; parasitic phenomenon; silicon data; wafer level; Educational institutions; Layout; Logic gates; Photonic band gap; Threshold voltage; Transistors; Voltage measurement; Analog design; gate voltage matching; hump effect; weak inversion;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2013.2237778
  • Filename
    6461399
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=55117