Title :
Activation Energies
of Failure Mechanisms in Advanced NAND Flash Cells for Different Generations and Cycling
Author :
Kyunghwan Lee ; Myounggon Kang ; Seongjun Seo ; Duckseoung Kang ; Shinhyung Kim ; Dong Hua Li ; Hyungcheol Shin
Author_Institution :
Inter-Univ. Semicond. Res. Center, Seoul Nat. Univ., Seoul, South Korea
Abstract :
The conventional temperature-accelerated lifetime test method of NAND Flash memory does not follow the Arrhenius model, as various failure mechanisms occur concurrently. We completely separated three main failure mechanisms and extracted each activation energy (Ea) value in three generations (A, B, C) of advanced NAND Flash memory. We compared and analyzed each value of Ea of the three main mechanisms with different device generations and cycling times. The results confirmed that each failure mechanism follows the Arrhenius law. The extracted Ea values of the detrapping mechanism were almost the same (Ea ~ 1.0 eV) regardless of the generation or the cycling times because they are determined by the rate of change of the detrapping probability of each trapped electron according to the baking temperature, not the surface area or trap density. However, the Ea value of the trap-assisted tunneling (TAT) mechanism is dependent on the generation and cycling times. Both the dominant trap energy levels and the average distance between the traps in the oxide layer have a strong impact on the Eavalue of the TAT mechanism. The interface trap recovery mechanism has very small time-constant (τ), and its activation energy is very small (Ea ~ 0.2 eV).
Keywords :
NAND circuits; failure analysis; flash memories; integrated circuit reliability; integrated circuit testing; interface states; life testing; probability; Arrhenius law; Arrhenius model; TAT mechanism; activation energy value; advanced NAND flash cells; baking temperature; detrapping mechanism; detrapping probability; device cycling time; device generation; dominant trap energy levels; failure mechanism; interface trap recovery mechanism; oxide layer; temperature-accelerated lifetime test method; time constant; trap-assisted tunneling mechanism; Electron traps; Energy states; Failure analysis; Flash memory; Lifetime estimation; Temperature distribution; Temperature measurement; Activation energy $(E_{a})$; NAND Flash; P/E cycling; detrapping mechanism; failure mechanism; interface trap recovery; retention time $(t_{R})$; trap-assisted tunneling (TAT);
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2013.2241065