An automatically generated VHDL-code of a Delta-Sigma-Modulator

In this paper an automatically generated VHDL-Code of a Delta-Sigma-Modulator for a digital design-flow is presented. For the verification of the design-flow, an example system - a digital 4^th-order Delta-Sigma-Modulator - in a standard 0.35μm technology is manufactured. As a proof of concept the simulation is compared to the measurement of this system. The fundamental element, the VHDL-Code of the Delta-Sigma-Modulator, is automatically generated with Matlab. So a design-flow in a single tool for a digital Delta-Sigma-Modulator is given from the system base to a hardware description language. This automatically generated VHDL-Code will be directly used in the further Synthesis/Layout-Tool-Chain.