DocumentCode :
552320
Title :
Design of a 10-bit 40 MS/s pipelined ADC using 1.5-bit with current-mode reference shifting
Author :
Pacheco, João ; Paulino, Nuno ; Figueiredo, Michael ; Goes, João
Author_Institution :
Dept. de Eng. Electrotec., Univ. Nova de Lisboa, Caparica, Portugal
fYear :
2011
fDate :
16-18 June 2011
Firstpage :
299
Lastpage :
302
Abstract :
This paper presents a 1.5-bit MDAC circuit to be used in pipeline ADCs which employs a switched-current source to perform the reference shifting of the MDAC (the 1.5-bit digital-to-analog function). In the proposed circuit, the two single-ended reference voltage sources that are traditionally used (VREFP and VREFN), are replaced by a switched-current source. To evaluate and compare the performance of the proposed circuit, two 10-bit 40 MS/s ADCs, one using the traditional switched-capacitor (SC) MDAC and the other using the proposed MDAC, are designed. Simulation results show that the performance of the ADC with the proposed MDAC is enhanced since the power needed for the current sources is smaller than the power supplied by the reference voltage sources. Moreover, the proposed circuit does not require any reference voltage buffer, which can be difficult to design with relatively low power dissipation.
Keywords :
analogue-digital conversion; reference circuits; switched capacitor networks; current mode reference shifting; pipelined ADC; power dissipation; single ended reference voltage sources; switched capacitor; Capacitors; Clocks; Computer architecture; Pipeline processing; Power dissipation; Simulation; Switching circuits; CMOS Technology; Current-Mode; Switched-Capacitor; pipeline ADC;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference
Conference_Location :
Gliwice
Print_ISBN :
978-1-4577-0304-1
Type :
conf
Filename :
6015929
Link To Document :
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