Non-linear modelling of resolve time in D-latch circuits

The time needed by a bistable circuit to reach its stable state, when the initial state of the circuit is close to its metastable point, can vary substantially - causing malfunction of encompassing systems, expecting limited resolve time. The paper presents novel models of resolve time for static D-latch circuits - to estimate the metastability effect more accurately, and set design margins properly. The models consider nonlinearity of both the positive feedback loop and also that of initial condition setting for switching process. Accuracy advantage over the commonly used model is demonstrated with measurements and simulation of different D-latch circuits (both buffered and unbuffered ones).