A matrix-based voltage range estimation method using linearized operating points

This paper presents an extended method for feasible voltage range estimation in analog CMOS circuits from a single DC operating point simulation. Devices are modeled as linearized operating points (LOPs) which relate their terminal voltages and saturation constraints by arbitrary linear relations. This improves accuracy for short channel MOS devices and allows consideration different types of devices. A generalized symbolic matrix-based method calculates feasible voltage ranges and allows detailed identification of constraint violations with respect to the contributing devices. The method is implemented in a state-of-the-art custom design flow and its benefits are illustrated using example circuit analyses.