DocumentCode :
552350
Title :
On-chip jitter measurement architecture using a delay-locked loop with vernier delay line, to the order of giga hertz
Author :
Abdel-Hafeez, Saleh ; Harb, Shadi M. ; Lee, Ken M.
Author_Institution :
Fac. of Comput. & Inf. Technol., Jordan Univ. of Sci. & Technol., Irbid, Jordan
fYear :
2011
fDate :
16-18 June 2011
Firstpage :
502
Lastpage :
506
Abstract :
In this paper, we present an enhanced architecture circuit design for embedded jitter measurement using the Vernier delay method with a single delay locked loop (DLL) structure, which characterizes the jitter in the order of picoseconds. The jitter measurement is realized by two delay chains feeding into the clock and data lines of a series of detector components known as a Vernier delay line (VDL). The matching of various delay elements is adjusted on-the-fly by an enhanced structure of a DLL feedback topology. Thereby, reducing the effect of the intrinsic gate delay variations due to process, voltage, temperature (PVT) changes; a limitation that reflects a major drawback of the VDL structure, and requires a large cost of design layout complexity. The nature of the design topology uses a small silicon area with a scalable jitter analyzer circuitry, which is used to collect the jitter on the data signal. The design nature is synthesizable using the field-programmable gate-array (FPGA) implementation. The proposed design estimates a silicon area of 0.074mm2, and HSPICE simulation results indicate a timing resolution of 25ps in a 0.18μm TSMC CMOS process.
Keywords :
CMOS integrated circuits; SPICE; delay lines; delay lock loops; elemental semiconductors; field programmable gate arrays; silicon; timing jitter; DLL feedback topology; FPGA; HSPICE simulation; Si; TSMC CMOS process; Vernier delay line; architecture circuit design; clock; field programmable gate array; intrinsic gate delay variations; on-chip jitter measurement; scalable jitter analyzer circuitry; silicon; single delay locked loop; size 0.18 mum; time 25 ps; Integrated circuits; DLL; FPGA; Giga Hertz; Jitter measurement; Single-One detector; Timing Skew; VDL;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference
Conference_Location :
Gliwice
Print_ISBN :
978-1-4577-0304-1
Type :
conf
Filename :
6015974
Link To Document :
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