Analysis of selected methods for CMOS integrated circuit design for yield optimization

Two approaches for CMOS integrated circuit design taking into account a process variability and oriented towards optimization of a parametric yield have been reviewed. These are a method based on cumulative distribution function, and a so-called worst-case distance method, based on random variable probability density function. In both methods there is an assumption that CMOS process statistical data are expressed in terms of so-called process parameter distributions. Thus the design centering is done via layout parameter tuning. The first approach relies on maximizing the probability that random variables corresponding to IC performances remain within the performance boundaries. In the second method the design is centered by analysis and optimization of given IC performance position and orientation vs constraints imposed by design performance boundaries. Also, a methodology for statistical characterization of CMOS process has been briefly described. Finally, both design centering methods have been compared, and their operation has been illustrated using CMOS inverter and opamp cases.