MOSFET modeling for simulation, design and optimization of infrared CMOS image sensors working at cryogenic temperature

This paper is a review on research efforts in CEA-Leti on compact modeling of MOS transistors for simulation of mixed-signal circuits working at cryogenic temperatures (0.3 K, 4.2 K, 77 - 200 K). Specific and non-specific physical effects are observed when cooling transistors of CMOS technologies ranging from 0.7 μm down to 0.18 μm. Weak and moderate inversion regions are emphasized, as they are crucial for design of ultra low power circuits due to cryogenic constraints. These results will provide helpful guidelines for design and optimization of complex infrared CMOS imagers for high performance.