Title :
A compact model of VeSFET capacitances
Author :
Kasprowicz, Dominik
Author_Institution :
Inst. of Microelectron. & Optoelectron., Warsaw Univ. of Technol., Warsaw, Poland
Abstract :
This paper introduces a compact model of the gate-to-source/drain capacitance of the VeSFET (Vertical-Slit Field-Effect Transistor). The model modifies an existing substrate-potential model to calculate the charge in the VeSFET´s complex structure. It is valid for arbitrary biases on the device´s two independent gates. Good agreement with numerical simulations is demonstrated.
Keywords :
capacitance; field effect transistors; semiconductor device models; VeSFET capacitance compact model; gate-to-source/drain capacitance; substrate potential model; vertical slit field effect transistor; Capacitance; Integrated circuit modeling; Logic gates; Mathematical model; Semiconductor device modeling; Semiconductor process modeling; Substrates; VeSFET; VeSTIC; capacitance model; compact model; dual-gate device; independent gates;
Conference_Titel :
Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference
Conference_Location :
Gliwice
Print_ISBN :
978-1-4577-0304-1
