A study on cell-level routing for VeSFET circuits

In this paper, we study the inter-cell routing of circuits implemented with VeSFET transistors. VeSFET-based cells have footprint significantly smaller than their CMOS counterparts and their layouts affect the inter-cell routability. We observe that cell footprint scaling leads to wire lengths reduction only when a sufficient number of inter-cell metal layers is available. Otherwise, the inter-cell white space needed for routing obliterates the potential benefits of footprint scaling. VeSFET-based circuits may benefit from routing on both sides of the transistor layer.