Title :
A 16-Core Processor With Shared-Memory and Message-Passing Communications
Author :
Zhiyi Yu ; Ruijin Xiao ; Kaidi You ; Heng Quan ; Peng Ou ; Zheng Yu ; Maofei He ; Jiajie Zhang ; Yan Ying ; Haofan Yang ; Jun Han ; Xu Cheng ; Zhang Zhang ; Ming´e Jing ; Xiaoyang Zeng
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Abstract :
A 16-core processor with both message-passing and shared-memory inter-core communication mechanisms is implemented in 65 nm CMOS. Message-passing communication is enabled in a 3 × 6 Mesh packet-switched network-on-chip, and shared-memory communication is supported using the shared memory within each cluster. The processor occupies 9.1 mm2 and operates fully functional at a clock rate of 750 MHz at 1.2 V and maximum 800 MHz at 1.3 V. Each core dissipates 34 mW under typical conditions at 750 MHz and 1.2 V while executing embedded applications such as an LDPC decoder, a 3780-point FFT module, an H.264 decoder and an LTE channel estimator.
Keywords :
CMOS integrated circuits; decoding; low-power electronics; message passing; network-on-chip; packet switching; parity check codes; shared memory systems; 16-core processor; 3780-point FFT module; CMOS process; H.264 decoder; LDPC decoder; LTE channel estimator; frequency 750 MHz; frequency 800 MHz; message-passing communications; packet-switched network-on-chip; power 34 mW; shared-memory intercore communication; size 65 nm; voltage 1.2 V; voltage 1.3 V; Clocks; Memory management; Multicore processing; Registers; Scalability; Voltage-controlled oscillators; Chip multiprocessor; FFT; H.264 decoder; LDPC decoder; LTE channel estimator; NoC; SIMD; cluster-based; inter-core communication; inter-core synchronization; message-passing; multi-core; network-on-chip; shared-memory;
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2013.2283693
