Title :
Circuit for reducing devices voltage stress due to DC-link capacitor voltage ripple in a Neutral-Point-Clamped inverter
Author :
Orfanoudakis, G.I. ; Sharkh, S.M. ; Yuratich, M.A.
Author_Institution :
Sch. of Eng. Sci., Univ. OF SOUTHAMPTON, Southampton, UK
fDate :
Aug. 30 2011-Sept. 1 2011
Abstract :
The paper presents a circuit that reduces the voltage stress caused by DC-link capacitor voltage ripple on the switching devices of a three-level Neutral-Point-Clamped (NPC) inverter. The circuit is capable of halving the amplitude of the voltage ripple seen by the inverter devices. It is proposed as an alternative to over-sizing the inverter´s DC-link capacitors, or using capacitor-balancing PWM strategies that increase the switching frequency and associated losses. The structure and operation of the circuit are described and the ratings of its components are determined. The benefit it offers is compared to that of existing solutions, based on an example NPC inverter design. The results, verified using MATLAB-Simulink, indicate that the circuit can outperform other proposed balancing circuits, halve the DC-link capacitance and cover cases where the switching frequency cannot be increased.
Keywords :
PWM invertors; capacitance; capacitors; power supply quality; switching convertors; DC-link capacitance; MATLAB-Simulink; NPC inverter design; capacitor-balancing PWM strategy; device voltage stress circuit; inverter DC-link capacitor voltage ripple; inverter device; switching device; switching frequency; three-level neutral point clamped inverter; voltage ripple; Capacitance; Capacitors; Inverters; Modulation; Oscillators; Switches; Switching circuits; DC-link capacitor balancing; Neutral-Point-Clamped (NPC) inverter; Voltage Source Inverters (VSI);
Conference_Titel :
Power Electronics and Applications (EPE 2011), Proceedings of the 2011-14th European Conference on
Conference_Location :
Birmingham
Print_ISBN :
978-1-61284-167-0
Electronic_ISBN :
978-90-75815-15-3
