DocumentCode
553735
Title
FlePS: A power interface for Power Hardware In the Loop
Author
Benigni, A. ; Helmedag, Alexander ; Abdalrahman, A.M.E. ; Pilatowicz, G. ; Monti, Antonello
Author_Institution
E.ON Energy Res. Center, RWTH Aachen Univ., Aachen, Germany
fYear
2011
fDate
Aug. 30 2011-Sept. 1 2011
Firstpage
1
Lastpage
10
Abstract
Power Hardware In the Loop (PHIL) is a recognized technique to extend Hardware In the Loop tests to power level by enforcing conservation of energy at the connection between real and virtual portions of the system under test. In this paper we present the design of a flexible hardware interface to perform PHIL testing: some experimental results are also presented.
Keywords
automatic test equipment; embedded systems; energy conservation; power electronics; power system simulation; FlePS; PHIL testing; energy conservation; flexible hardware interface; flexible power simulator; power hardware in the loop; power interface; Capacitors; Hardware; Insulated gate bipolar transistors; Junctions; Real time systems; Switches; Switching frequency; Power Electronics; Power System Simulation; Real Time System; Virtual prototyping;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Electronics and Applications (EPE 2011), Proceedings of the 2011-14th European Conference on
Conference_Location
Birmingham
Print_ISBN
978-1-61284-167-0
Electronic_ISBN
978-90-75815-15-3
Type
conf
Filename
6020594
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