Title :
The design and simulation of array multiplier improved with pipeline techniques
Author :
Zhong-Ye Yang ; Jin-qiu Xiao
Author_Institution :
Dept. of Electron. & Inf. Eng., Suzhou Univ. of Sci. & Technol., Suzhou, China
Abstract :
In this paper, the time complexity of two´s complement Array Multiplier has been analyzed. Based on the analysis, a method for improving the performance of Array Multiplier with pipeline has been discussed, and the modeling of it has been built with VHDL. Furthermore, the conclusion of Simulation and function verification has been given.
Keywords :
hardware description languages; parallel processing; pipeline arithmetic; VHDL; array multiplier; design; function verification; pipeline techniques; simulation; Adders; Arrays; Clocks; Delay; Latches; Logic gates; Pipelines; Array Multiplier; Pipeline; VHDL;
Conference_Titel :
Electronic and Mechanical Engineering and Information Technology (EMEIT), 2011 International Conference on
Conference_Location :
Harbin, Heilongjiang
Print_ISBN :
978-1-61284-087-1
DOI :
10.1109/EMEIT.2011.6023995
