A Demand-Based FTL Scheme Using Dualistic Approach on Data Blocks and Translation Blocks

Using NAND flash memory as a storage device is in the limelight due to its many attractive features, but it also has vulnerable points. Specifically, as NAND flash memory does not allow the overwrite of data in the same place, it performs out-place-update, which requires the address translation table between logical and physical addresses. Due to the ever growing size of NAND flash memory, keeping the whole address translation table in SRAM is becoming increasingly a serious problem. In this paper, we present three management schemes to reduce the SRAM space in address translation but also guarantee the performance. First, we store data in NAND flash memory by using a page level mapping scheme. A page level mapping scheme allows NAND flash memory to store data in any place, and thus we can improve the storage efficiency. Second, we keep only a small amount of address translation entries in the page address translation cache (PATC) to reduce the size of SRAM. The other address translation entries that are in NAND flash memory will be loaded in SRAM on demand. Furthermore, we manage an address translation table in NAND flash memory by using a hybrid mapping scheme to reduce the size of translation block mapping directory (TBMD). Third, we take advantage of PATC to identify data whether they are hot or cold. By separating hot data from cold data using PATC, we prolong NAND flash memory´s lifespan and reduce garbage collection time without any additional cost. Integrating these three schemes leads to the improved read response time compared to the state-of-the-art FTL algorithm, DFTL, by up to 56.9% though it uses only 10% of SRAM. Moreover, if the proposed scheme uses the same amount of SRAM, the response time is improved and the average number of valid pages in a victim block also decreases by up to 67% by efficiently separating hot data from cold data.