DocumentCode :
556082
Title :
Investigation of reduced models of capacitive loaded interconnects for the high-speed SI applications
Author :
Ravelo, B. ; Eudes, T. ; Jastrzebski, A.K.
Author_Institution :
Grad. Sch. of Eng., IRSEEM, ESIGELEC, St. Etienne du Rouvray, France
fYear :
2011
fDate :
26-30 Sept. 2011
Firstpage :
357
Lastpage :
361
Abstract :
The paper presents a reduced modeling method of a microstrip interconnect for the signal integrity (SI) applications. First- and second- order polynomial models of interconnects based on distributed RLCG model of a transmission line are investigated. Model accuracies are compared with exact circuit/EM co-simulations for a typical high-speed 20 μm-wide microstrip interconnect on Alumina substrate for varying interconnect lengths between 1 and 10 mm and for signal data rates between 1 and 10 Gbit/s. It is shown that the second-order model has a relative amplitude and phase errors lower than 1% from DC to 40 GHz. Also, the second-order model predicts very well the time-domain response to a pulse signal, making it suitable for the accurate prediction of the degradation of RF/digital signals in the high-speed integrated systems.
Keywords :
alumina; integrated circuit interconnections; polynomials; transmission lines; alumina substrate; capacitive loaded interconnects; distributed RLCG model; first-order polynomial model; microstrip interconnect; reduced modeling method; second-order polynomial model; signal integrity application; transmission line; Data models; Electromagnetic compatibility; Integrated circuit interconnections; Integrated circuit modeling; Load modeling; Table lookup; Transfer functions; RLCG-model; Signal integrity (SI); high-speed digital system; mirostrip interconnects; transient analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
EMC Europe 2011 York
Conference_Location :
York
Print_ISBN :
978-1-4577-1709-3
Type :
conf
Filename :
6078600
Link To Document :
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