Comparative study of the effects of coalesced and distributed solder die attach voids on thermal resistance of packaged semiconductor device

Solder thermal interface materials are often used in power semiconductors to enhance heat dissipation from silicon die to the heat spreader. Nonetheless, the presence of voids in the die bond layer impedes heat flow and thus increases the chip junction temperature. Such voids which form easily in the solder joint during solder reflow process at manufacturing stage are primarily occasioned by out-gassing phenomenon. Three-dimensional finite element analysis is employed to investigate the thermal effects of lead-free solder void percentages and configurations on packaged semiconductor device. The thermal resistance for each voiding case is calculated to evaluate the thermal response of the resultant electronic package. The results show that for equivalent void percentage, thermal resistance increases more for large coalesced type voids in comparison to the small distributed void configurations. The results would assist packaging and design engineers in setting criteria for assessments of the thermal impacts of different solder void patterns.