DocumentCode :
556392
Title :
3D electro-thermal simulations of analog ICs carried out with standard CAD tools and Verilog-A
Author :
Krencker, Jean-Christophe ; Kammerer, Jean-baptiste ; Hervé, Yannick ; Hébrard, Luc
Author_Institution :
Inst. d´´Electron. du Solide et des Syst. (InESS), Strasbourg, France
fYear :
2011
fDate :
27-29 Sept. 2011
Firstpage :
1
Lastpage :
4
Abstract :
High power density in integrated systems creates rises of temperature and gradient across the chip that can deteriorate the electrical performances of the system. In 3D stacked technologies, on chip power density will be even more important while heat spreading will be reduced leading to more thermal issues. Thus, it is very important for designers to have a powerful and reliable electro-thermal simulator. This paper presents a designer friendly efficient direct electro-thermal simulator integrated in the Cadence® environment that couples the electrical schematic to its thermal network. The comparison between experimental and simulation results of a test chip are given to validate the simulator.
Keywords :
analogue integrated circuits; hardware description languages; integrated circuit design; 3D electro-thermal simulation; 3D stacked technology; CAD tool; Cadence; Verilog-A; analog IC; high power density; Hardware design languages; Heating; Integrated circuit modeling; Solid modeling; Thermal analysis; Three dimensional displays;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Thermal Investigations of ICs and Systems (THERMINIC), 2011 17th International Workshop on
Conference_Location :
Paris
Print_ISBN :
978-1-4577-0778-0
Type :
conf
Filename :
6081044
Link To Document :
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