Title :
Design intent utilization for lithography compliance check and layout refinement to improve manufacturability
Author :
Kobayashi, Sachiko ; Ikeuchi, Atsuhiko ; Kimura, Kazunari ; Kotani, Toshiya ; Tanaka, Satoshi ; Kyoh, Suigen ; Maeda, Shimon ; Inoue, Soichi
Abstract :
A collection of slides from the authors conference presentation about the design intent utilization for lithography compliance check and layout refinement to improve manufacturability is presented.
Keywords :
lithography; semiconductor device manufacture; design intent utilization; layout refinement; lithography compliance check; manufacturability; Data mining; Design methodology; Lithography; Loss measurement; Timing; Wires;
Conference_Titel :
Semiconductor Manufacturing (ISSM) and e-Manufacturing and Design Collaboration Symposium (eMDC), 2011 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4577-1647-8
