Implementation of a receiver for an EPC tag emulator for performance evaluation

In this paper the receiver path of an EPC Class- 1 Gen-2 conform RF identification (RFID) Tag Emulator at 868 MHz is presented. The underlying hardware avoids the disadvantages of common tag emulators which emulate the logical behavior only. The implemented EPC Tag Emulator allows the precise emulation of the physical behavior of an UHF RFID tag. Therefore, it can handle worst case test scenarios for reader performance evaluation. In particular, the backlink frequency (BLF) of each backscattered symbol as well as the tag to reader link timing can be varied beyond the EPC specifications. The continuously changeable complex input reflection coefficient allows the investigation of the influence of a changing phase and/or a Doppler shift on the reader and the evaluation of the reader´s receiver sensitivity. The bit decoder which is implemented in FPGA hardware is discussed in detail in this paper. The data symbols are decoded autonomously after a correct Preamble/Framesync is detected. Therefore, the bit decoder unit cross-checks the timing values and an undesired command is discarded. A valid Preamble/Framesync starts the command parser which accesses the bit decoder unit. The command parser and the protocol stack are handled by the microcomputer unit in the higher layers in software. The protocol stack includes all mandatory commands. The receiver path is tested under real conditions and the sensitivity of Pτ_in = -29.3dBm is much better than the sensitivity of common tag ICs. Furthermore, it is shown that the tag emulator replies faster than specified by the tag to reader (T⇒R) link timing. The reader´s behavior on a faster tag reply can be investigated.