• DocumentCode
    55845
  • Title

    An ILP-Based Routing Algorithm for Pin-Constrained EWOD Chips With Obstacle Avoidance

  • Author

    Jia-Wen Chang ; Sheng-Han Yeh ; Tsung-wei Huang ; Tsung-Yi Ho

  • Author_Institution
    Dept. of Comput. Sci. & Inf. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
  • Volume
    32
  • Issue
    11
  • fYear
    2013
  • fDate
    Nov. 2013
  • Firstpage
    1655
  • Lastpage
    1667
  • Abstract
    Electrowetting-on-dielectric (EWOD) chips have become the most popular actuators, particularly for droplet-based digital microfluidic biochip (DMFB) systems. In order to enable the electrical manipulations, wire routing is a key problem in designing EWOD chips. Unlike traditional very-large-scale-integration (VLSI) routing problems, in addition to routing-path establishment on signal pins, the pin-constrained EWOD-chip routing problem must address the issue of signal sharing for pin-count reduction under a practical constraint posed by a limited pin-count supply. Moreover, EWOD-chip designs might incur several obstacles in the routing region due to embedded devices for specific fluidic protocols. However, no existing work considers the EWOD-chip routing with obstacles and, therefore, lots of manual design efforts are involved. To remedy this insufficiency, we propose in this paper the first routing algorithm for pin-constrained EWOD chips with obstacle avoidance. The proposed algorithm, based on effective integer-linear-programming (ILP) formulation as well as efficient routing framework, can achieve high routability with a low design complexity. Experimental results based on real-life chips with obstacles demonstrate the high routability of proposed algorithm for pin-constrained EWOD chips with obstacle avoidance.
  • Keywords
    integer programming; lab-on-a-chip; linear programming; microfluidics; network routing; ILP based routing algorithm; droplet based digital microfluidic biochip systems; electrowetting on dielectric chips; high routability; integer linear programming formulation; manual design efforts; obstacle avoidance; pin constrained EWOD chips; pin count reduction; real life chips; signal sharing; wire routing; Algorithm design and analysis; Electrodes; Pins; Routing; System-on-chip; Wires; Wiring; Digital microfluidic biochips; integer linear programming; pin-constrained; routing;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2013.2269767
  • Filename
    6634553