A fully integrated low phase noise, fast locking, 31 to 34.9 GHz dual-loop PLL

A fully integrated dual loop PLL with ultra-low phase noise and fast lock time is presented. The topology combines a frequency acquisition and a phase-locked hold loop. The phase-locked hold loop includes a mixer-type phase detector (PD), a 32:1 frequency divider, an active loop filter and a VCO. A 3-state phase-frequency detector (PFD) is designed for the frequency acquisition loop. The chip was implemented in a 0.8 μm SiGe HBT technology. The frequency locking range varies from 31 GHz to 34.9 GHz. The output phase noise is around -111 dBc/Hz at 1 MHz offset. The frequency and phase lock time is less than 0.6 μs.