A fully integrated low phase noise, fast locking, 31 to 34.9 GHz dual-loop PLL

Author

Gai, Xiaolei ; Trasser, Andreas ; Schumacher, Hermann

Author_Institution

Inst. of Electron Device & Circuits, Univ. of Ulm, Ulm, Germany

fYear

2011

fDate

10-11 Oct. 2011

Firstpage

648

Lastpage

651

Abstract

A fully integrated dual loop PLL with ultra-low phase noise and fast lock time is presented. The topology combines a frequency acquisition and a phase-locked hold loop. The phase-locked hold loop includes a mixer-type phase detector (PD), a 32:1 frequency divider, an active loop filter and a VCO. A 3-state phase-frequency detector (PFD) is designed for the frequency acquisition loop. The chip was implemented in a 0.8 μm SiGe HBT technology. The frequency locking range varies from 31 GHz to 34.9 GHz. The output phase noise is around -111 dBc/Hz at 1 MHz offset. The frequency and phase lock time is less than 0.6 μs.

Keywords

Ge-Si alloys; active filters; frequency dividers; heterojunction bipolar transistors; millimetre wave detectors; millimetre wave oscillators; phase locked loops; phase noise; voltage-controlled oscillators; 3-state phase-frequency detector; SiGe; SiGe HBT technology; VCO; active loop filter; frequency 31 GHz to 34.9 GHz; frequency acquisition; frequency divider; frequency locking; fully integrated dual-loop PLL; fully integrated low phase noise; mixer-type phase detector; phase-locked hold loop; size 0.8 mum; ultra-low phase noise; Frequency conversion; Frequency measurement; Phase frequency detector; Phase locked loops; Phase noise; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Integrated Circuits Conference (EuMIC), 2011 European

Conference_Location

Manchester

Print_ISBN

978-1-61284-236-3

Type

conf

Filename

6102830