Title :
Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation
Author :
Carlson, Trevor E. ; Heirman, Wim ; Eeckhout, Lieven
Author_Institution :
ELIS Dept., Ghent Univ., Ghent, Belgium
Abstract :
Two major trends in high-performance computing, namely, larger numbers of cores and the growing size of on-chip cache memory, are creating significant challenges for evaluating the design space of future processor architectures. Fast and scalable simulations are therefore needed to allow for sufficient exploration of large multi-core systems within a limited simulation time budget. By bringing together accurate high-abstraction analytical models with fast parallel simulation, architects can trade off accuracy with simulation speed to allow for longer application runs, covering a larger portion of the hardware design space. Interval simulation provides this balance between detailed cycle-accurate simulation and one-IPC simulation, allowing long-running simulations to be modeled much faster than with detailed cycle-accurate simulation, while still providing the detail necessary to observe core-uncore interactions across the entire system. Validations against real hardware show average absolute errors within 25% for a variety of multi-threaded workloads; more than twice as accurate on average as one-IPC simulation. Further, we demonstrate scalable simulation speed of up to 2.0 MIPS when simulating a 16-core system on an 8-core SMP machine.
Keywords :
cache storage; digital simulation; multiprocessing systems; 16-core system; 8-core SMP machine; Sniper; abstraction level exploration; core larger numbers; core-uncore interactions; cycle-accurate simulation; hardware design space; high-performance computing; interval simulation; multithreaded workloads; on-chip cache memory; one-IPC simulation; parallel multicore simulation; processor architectures; Accuracy; Analytical models; Kernel; Load modeling; Multicore processing; Synchronization; Interval simulation; interval model; multi-core processor; performance modeling;
Conference_Titel :
High Performance Computing, Networking, Storage and Analysis (SC), 2011 International Conference for
Conference_Location :
Seatle, WA
Electronic_ISBN :
978-1-4503-0771-0