Measurements and co-simulation of on-chip and on-board AC power noise in digital integrated circuits

Power noise of an integrated circuit (IC) chip is dominantly characterized by the frequency-domain impedance of a chip-package-board integrated power delivery network (PDN) and the operating frequency of circuits. A 65 nm CMOS chip embedding a high precision on-chip waveform capture clearly exhibits the relation of AC power noise components with the parallel resonance seen from on-chip digital circuits. On-chip voltage noise measured by the waveform capture and on-board current noise by a near-field magnetic field probe are also experimentally related to each other, in the context of the resonance. In addition, fast power current analysis uses a capacitor charging model of digital circuits and embodies accurate co-simulation of AC power noise, along with a chip-package-board integrated PDN impedance model. A predictive measure in the design of IC chips is provided toward on-chip power supply integrity (PSI) as well as off-chip electromagnetic compatibility (EMC).