Title :
On-chip power integrity evaluation system
Author :
Nabeshima, Yoshitaka ; Oizono, Yoshiaki ; Okumura, Takafumi ; Sudo, Toshio
Author_Institution :
Shibaura-Inst. of Technol., Tokyo, Japan
Abstract :
Power supply disturbance excited by simultaneous switching output (SSO) circuits or core circuits is a serious issue in a system-in-package (SIP), especially in 3D stacked die package, because much more I/O circuits and core circuits excited simultaneously in synchronized with clock edges than the case of single die package. Therefore, decoupling schemes in such SiP´s must be carefully designed including on-chip capacitance as well as off-chip capacitance so as to reduce the impedance of power distribution network (PDN) as low as possible up to high frequency range. In this paper, an on-chip power integrity evaluation system has been established using a test chip with both noise generating circuits and monitoring circuits for on-chip power supply noise. On-chip power integrity has been examined and compared for the cases with and without on-chip capacitance and for the various embedded capacitors inside an interposer.
Keywords :
distribution networks; system-in-package; three-dimensional integrated circuits; 3D stacked die package; I/O circuits; PDN; SIP; SSO circuits; core circuits; decoupling schemes; embedded capacitors; monitoring circuits; noise generating circuits; off-chip capacitance; on-chip capacitance; on-chip power integrity evaluation system; on-chip power supply noise; power distribution network; power supply disturbance; simultaneous switching output circuits; single die package; system-in-package; test chip; Capacitance; Capacitors; Monitoring; Noise; Power supplies; Semiconductor device measurement; System-on-a-chip; On-chip Power Integrity; Power supply disturbance; interposer; power distribution network; system-in-package;
Conference_Titel :
Electromagnetic Compatibility of Integrated Circuits (EMC Compo), 2011 8th Workshop on
Conference_Location :
Dubrovnik
Print_ISBN :
978-1-4577-0862-6