An FPGA based hardware accelerator for real time video segmentation system

Video Segmentation is the basic requirement for applications such as video surveillance, traffic management and medical imaging. The high computation power must be provided to support this operation. This paper discuss on design and implementation of hardware accelerator for video segmentation. The algorithm of Sobel edge detection operator is used to develop this hardware accelerator. To develop hardware accelerator datapath architecture the management of memory access is deployed and architecture based pipeline are made with the potential improvements in acceleration to the read data pixel from memory. In addition, a finite state machine is used to ensure the hardware accelerator controls the sequence of derivative computation, the write and read operations. System Integration uses NIOS II processor and Avalon bus interfacing. The hardware accelerator design was implemented on an Altera FPGA development board and has managed to achieve a video rate of 30 frames per second as required by NTSC standard definition video. The architecture core for memory access has succeeded to reduce memory bandwidth utility by 75%.