Title :
Verification system for SoC HDL-code
Author :
Litvinova, Eugenia ; Hahanova, Anna ; Gorobets, Alexander ; Priymak, Aleksey
Abstract :
Assertion-based models and methods for the verification and diagnosis of HDL-code functional failures, which make possible to reduce considerably time-to-market of software and hardware, are developed.
Keywords :
program diagnostics; program verification; system-on-chip; HDL-code functional failure diagnosis; HDL-code functional failure verification; SoC HDL-code; assertion-based models; hardware time-to-market; software time-to-market; verification system; IP networks; HDL-model; Infrastructure IP; testing; verification;
Conference_Titel :
Modern Problems of Radio Engineering Telecommunications and Computer Science (TCSET), 2012 International Conference on
Conference_Location :
Lviv-Slavske
Print_ISBN :
978-1-4673-0283-8
