• DocumentCode
    56346
  • Title

    A Study of Cu/CuMn Barrier for 22-nm Semiconductor Manufacturing

  • Author

    Sze-Ann Wu ; Yi-Lung Cheng ; Chia-Yang Wu ; Wen-Hsi Lee

  • Author_Institution
    Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
  • Volume
    14
  • Issue
    1
  • fYear
    2014
  • fDate
    Mar-14
  • Firstpage
    286
  • Lastpage
    290
  • Abstract
    The barrier properties of self-forming barrier are sensitive to the thickness, annealing temperature, annealing time, and impurity concentration of itself. In this paper, the properties of Cu/CuMn/ SiO2 bilayer structures were investigated, and an optimized thickness of Cu and CuMn alloy used as barrier layers in these bilayer structures was also determined. The bilayer structure could reduce the resistance of barrier and improve the surface morphology in electroplating process because Mn is easier to be corroded and oxidized than Cu in sulfuric acid. The electrical and material properties of Cu/CuMn/ SiO2 were studied. A diffusion barrier layer self-formed at the interface during annealing, and the growth behavior followed a logarithmic rate law. The microstructures of the metal films were analyzed by transmission electron microscopy (TEM) and then correlated with the electrical properties of the CuMn films. After annealing, the thermal stability of Cu/ CuMn films was better than single Cu film and CuMn film. When Cu layer was capped, the Mn atoms diffused easily to the interface due to high chemical potential of the Cu layer. Thus, Mn atoms tend to move to SiO2, and the amount of surplus Mn atoms in Cu will reduce after heat treatment.
  • Keywords
    chemical interdiffusion; copper alloys; crystal microstructure; electroplating; heat treatment; manganese alloys; multilayers; semiconductor device manufacture; silicon compounds; surface morphology; thermal stability; transmission electron microscopy; Cu-CuMn barrier; Cu-CuMn-SiO2; CuMn; TEM; annealing temperature; annealing time; barrier layers; barrier properties; bilayer structures; diffusion barrier layer; electrical properties; electroplating process; heat treatment; impurity concentration; logarithmic rate law; material properties; microstructures; self-forming barrier; semiconductor manufacturing; size 22 nm; sulfuric acid; surface morphology; thermal stability; transmission electron microscopy; Annealing; Bilayer structures; Temperature measurement; Bilayer structure; CuMn; self-forming;
  • fLanguage
    English
  • Journal_Title
    Device and Materials Reliability, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1530-4388
  • Type

    jour

  • DOI
    10.1109/TDMR.2013.2262525
  • Filename
    6515175