MOS capacitance under punchthrough conditions

A shallow P-N junction parallel to the surface of a semiconductor can materially alter the C-V characteristic of an MOS structure. This paper is a discussion of the theory of such structures. The analysis is based on a numerical solution of the continuity equations for electrons and holes, and of Poisson´s equation in the presence of an applied ac signal as well as a dc gate voltage. The result of the calculation, for any given substrate doping profile, is a C-V characteristic for any given ac signal frequency. The most striking anomaly in the C-V characteristic occurs in the inversion region and is caused by a punch-through condition-that is, the merging of the gate-induced surface depletion region with the P-N junction depletion region. A simple equivalent circuit model, which does not require frequency-dependent capacitors, is proposed.