• DocumentCode
    563539
  • Title

    Design of short-channel ion-implanted mosfets with relatively deep junctions

  • Author

    Johnson, W.S. ; Peressini, P.P. ; Christie, K.H.

  • Author_Institution
    Syst. Products Div., IBM, Hopewell Junction, NY, USA
  • fYear
    1974
  • fDate
    9-11 Dec. 1974
  • Firstpage
    550
  • Lastpage
    553
  • Abstract
    This paper discusses design considerations for short-channel ion-implanted MOSFET devices with relatively deep junctions. Four device parameters are considered: threshold and transconductance reduction, sub-threshold turn-on, and punch-through. Channel-length variations affect power and performance tolerances of enhancement/ depletion logic NOR gates in two ways: first, down-level current is inversely proportional to channel length; second, short-channel physical effects cause variations in transconductance and threshold voltage. It will be demonstrated that threshold and transconductance variations in short-channel devices tend to offset one another so their net contributions to tolerances on such circuit parameters as switching speed, down-level power and down-level voltage are negligible. Dual-energy ion implantation is used in the channel regions - a shallow implant to control threshold voltage, and a deep implant to control punch-through voltage. Hence high-resistivity (15 ohm-cm) substrates can be used to reduce junction capacitance. These implants are shown to have little effect on short-channel properties other than punch-through because the doses are low. Low channel doping and the relatively deep junctions contribute to a desirable, steep device turn-on characteristic. We concluded that short-channel effects do not have to be avoided in the design of small MOSFET devices. Using ion implantation and careful design, circuit tolerances can be maintained allowing parameters such as junction depth to be optimized for other criteria such as metallurgy compatibility.
  • Keywords
    MOSFET; ion implantation; logic gates; channel length; channel-length variations; circuit parameters; depletion logic NOR gates; down-level current; dual-energy ion implantation; enhancement logic NOR gates; high-resistivity substrates; low channel doping; punch-through voltage; relatively deep junctions; short-channel ion-implanted MOSFET device design; short-channel physical effects; steep device turn-on characteristic; subthreshold turn-on; switching speed; threshold voltage; transconductance reduction; Abstracts; Capacitance; Junctions; Logic gates; Performance evaluation; Substrates;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting (IEDM), 1974 International
  • Conference_Location
    Washington, DC
  • ISSN
    0163-1918
  • Type

    conf

  • DOI
    10.1109/IEDM.1974.6219809
  • Filename
    6219809