A novel charge recycling approach to low-power circuit design

A novel charge-recycling scheme has been designed and implemented to demonstrate the feasibility of operating digital circuits using the charge scavenged from the leakage and dynamic load currents inherent to digital logic. The proposed scheme uses capacitors to efficiently recover the ground-bound charge and to subsequently boost the capacitor voltage to power up the source circuit. This recycling methodology has been implemented on a 12-bit Gray-code counter within a 12-bit multi-channel Wilkinson ADC. The circuit has been designed in 0.5μm BiCMOS and in 90nm CMOS processes. SPICE simulation results reveal a 46-53% average reduction in the energy consumption of the counter. The total energy savings including the control generation aggregates to an average of 26-34%.