DocumentCode
564177
Title
Strain relevance on the improvement of the 3T1D cell performance
Author
Amat, Esteve ; Almudéver, Carmen Garcia ; Aymerich, Nivard ; Canal, Ramon ; Rubio, Antonio
Author_Institution
Electron. Dept., Univ. Politec. de Catalunya (UPC), Barcelona, Spain
fYear
2012
fDate
24-26 May 2012
Firstpage
120
Lastpage
123
Abstract
3T1D-DRAM cell has been stated as a valid alternative to be implemented as a L1 memory cache and substitute 6T-SRAM, highly affected by variability. While scaling down capacitor-less DRAM cells is a challenging trend, in this paper we show how it can be compensated the scaling drawbacks through the channel strain of the cell devices and the proposal of new cell configurations to further enhance the circuit behavior.
Keywords
DRAM chips; SRAM chips; cache storage; 3T1D DRAM cell performance; 6T-SRAM; L1 memory cache; capacitor-less DRAM cell scaling; cell devices; channel strain; circuit behavior; strain relevance; Dielectrics; High K dielectric materials; Logic gates; Performance evaluation; Power demand; Random access memory; Strain; DRAM and temperature; strained channels;
fLanguage
English
Publisher
ieee
Conference_Titel
Mixed Design of Integrated Circuits and Systems (MIXDES), 2012 Proceedings of the 19th International Conference
Conference_Location
Warsaw
Print_ISBN
978-1-4577-2092-5
Type
conf
Filename
6226285
Link To Document