Title :
Chip implementation of AJC jitter reduction technology
Author :
Underhill, Michael J. ; Brodrick, James
Author_Institution :
Underhill Res., Lingfield, UK
Abstract :
The functions required for AJC jitter reduction technology have been assessed separately in a 3.5 micron `proof-of-concept´ (POC) CMOS chip. A simple AJC has been connected and shown to operate correctly and several improvements have been identified. In addition an experimental AJC has been simulated by a third party in 1.1 micron technology. Operation to over 1GHz was predicted and has been confirmed by the first results from a test chip.
Keywords :
CMOS integrated circuits; integrated circuit design; integrated circuit testing; jitter; phase locked loops; AJC; CMOS chip; anti-jitter circuit; chip implementation; jitter reduction technology; proof-of-concept; size 1.1 micron; size 3.5 micron; test chip; CMOS integrated circuits; Capacitors; Charge pumps; Jitter; Layout; Noise; Switches;
Conference_Titel :
Frequency and Time Forum (EFTF), 2006 20th European
Conference_Location :
Braunschweig
Print_ISBN :
978-1-4673-2642-1
