A hybrid and adaptive model for predicting register file and SRAM power using a reference design

This paper presents a predictive SRAM power model that reduces the changes required to adapt existing models to handle new circuit topologies, process corners, and design space exploration. Analytical equations model the impact of varying common characteristics such as bit-width, entries, segmentation, gating, and sizing while topology specific characteristics are captured empirically from a reference design. On distinct topologies of multi-port read, single- and dual-ended writes, this approach demonstrates an error of 5% and 7% for leakage and dynamic power respectively. We show that for a specific topology, any reference configuration can be used for accurate prediction.