Title :
Hardware Trojan horse benchmark via optimal creation and placement of malicious circuitry
Author :
Wei, Sheng ; Li, Kai ; Koushanfar, Farinaz ; Potkonjak, Miodrag
Author_Institution :
Comput. Sci. Dept., Univ. of California, Los Angeles, CA, USA
Abstract :
This paper proposes Hardware Trojan (HT) placement techniques that yield challenging HT detection benchmarks. We develop three types of one-gate HT benchmarks based on switching power, leakage power, and delay measurements that are commonly used in HT detection. In particular, we employ an iterative searching algorithm to find rarely switching locations, an aging-based approach to create ultra-low power HT, and a backtracking-based reconvergence identification method to determine the non-observable delay paths. The simulation results indicate that our HT attack benchmarks provide the most challenging representative test cases for the evaluation of side-channel based HT detection techniques.
Keywords :
circuit switching; integrated circuit design; invasive software; iterative methods; logic gates; search problems; HT detection benchmarks; aging-based approach; backtracking-based reconvergence identification method; delay measurements; hardware Trojan horse benchmark; hardware Trojan placement techniques; iterative searching algorithm; leakage power; nonobservable delay paths; optimal malicious circuitry creation; optimal malicious circuitry placement; side-channel based HT detection techniques; switching locations; switching power; ultra-low power HT; Benchmark testing; Delay; Integrated circuit modeling; Logic gates; Switches; Vectors; Hardware Trojan; benchmark; gate-level characterization; process variation;
Conference_Titel :
Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4503-1199-1