Library-aware resonant clock synthesis (LARCS)

Clock grids are often used in high-performance ASIC designs because of their low skew and robustness to variations. Resonant clock grids have the potential to reduce the power consumption of these high-performance clocks without sacrificing the skew and robustness of a clock grid. We present the first methodology to synthesize high-performance distributed resonant LC tank clock grids that utilize a pre-characterized inductor library. The use of a library reduces designer effort and total inductor area when compared with previous resonant clock grids while still attaining 59% power reduction and competitive skew when compared to traditional buffered clock grids.