Incremental power grid verification

Verification of the on-die power grid is a key step in the design of complex high-performance integrated circuits. For the very large grids in modern designs, incremental verification is highly desirable, because it allows one to skip the verification of a certain section of the grid (internal nodes)and instead, verify only the rest of the grid (external nodes). We propose an efficient approach for incremental verification in the context of vectorless constraints-based grid verification, under dynamic conditions. The traditional difficulty is that the dynamic case requires iterative analysis of both the internal and external sections. This has been previously overcome for simulation purposes, but we provide the first solution for verification, through two key contributions: 1)a bound on the internal nodes´ voltages is developed that eliminates the need for iterative analysis, and 2)a multi-port Norton approach is used to construct a reduced macromodel for the internal section. As a result, we demonstrate significant reductions in runtime, with speed-ups in the range of 3-8×, with negligible impact on accuracy.