Exploring sub-20nm FinFET design with Predictive Technology Models

Author

Sinha, Saurabh ; Yeric, Greg ; Chandra, Vikas ; Cline, Brian ; Cao, Yu

fYear

2012

fDate

3-7 June 2012

Firstpage

283

Lastpage

288

Abstract

Predictive MOSFET models are critical for early stage design-technology co-optimization and circuit design research. In this work, Predictive Technology Model files for sub-20nm multi-gate transistors have been developed (PTM-MG). Based on MOSFET scaling theory, the 2011 ITRS roadmap and early stage silicon data from published results, PTM for FinFET devices are generated for 5 technology nodes corresponding to the years 2012-2020 on the ITRS roadmap.

Keywords

MOSFET; integrated circuit design; scaling circuits; FinFET design; ITRS roadmap; MOSFET scaling theory; PTM-MG; circuit design research; early stage design-technology co-optimization; multigate transistors; predictive MOSFET models; predictive technology models; Capacitance; Delay; FinFETs; Integrated circuit modeling; Logic gates; Predictive models; FinFET; SPICE; multi-gate; predictive models; scaling theory;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE

Conference_Location

San Francisco, CA

ISSN

0738-100X

Print_ISBN

978-1-4503-1199-1

Type

conf

Filename

6241523

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=565141