Title :
AMOR: An efficient aggregating based model order reduction method for many-terminal interconnect circuits
Author :
Yangfeng Su ; Fan Yang ; Xuan Zeng
Author_Institution :
Microelectron. Dept., Fudan Univ., Shanghai, China
Abstract :
In this paper, we propose an efficient Aggregating based Model Order Reduction method (AMOR) for many-terminal interconnect circuits. The proposed AMOR method is based on the observation that those adjacent nodes of interconnect circuits with almost the same voltage can be aggregated together as a “super node”. Motivated by such an idea, we propose an efficient spectral partition algorithm in AMOR method to partition the nodes into groups with almost the same voltages. The reduced-order models are then obtained by aggregating the adjacent nodes within the same groups together as “super nodes” in AMOR method. The efficiency of AMOR method is not limited by the numbers of the terminals of the networks. Moreover, noticing that the aggregating procedure can be regarded as mapping the original problem into a coarse-grid problem in multigrid method, we propose a computation-efficient smoothing procedure to further improve the simulation accuracy of the reduced-order models. With such a strategy, the simulation accuracy of the reduced-order models can always be guaranteed. Numerical results have demonstrated that, without the smoothing procedure, the reduced-order models obtained by AMOR can still achieve higher simulation efficiency in terms of accuracy and CPU time than the reduced-order models obtained by the existing elimination based methods. With the smoothing procedure, the simulation accuracy of the reduced-order models can further be improved with several iterations.
Keywords :
integrated circuit interconnections; reduced order systems; AMOR method; CPU time; aggregating based model order reduction method; coarse-grid problem; computation-efficient smoothing procedure; elimination based method; many-terminal interconnect circuit; multigrid method; network terminal; reduced-order model; spectral partition algorithm; super node; Accuracy; Capacitors; Integrated circuit interconnections; Integrated circuit modeling; Partitioning algorithms; Reduced order systems; Resistors; Interconnect; Many-Terminal; Model Order Reduction;
Conference_Titel :
Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4503-1199-1