Title :
Cost-efficient buffer sizing in shared-memory 3D-MPSoCs using wide I/O interfaces
Author :
Foroutan, Sahar ; Sheibanyrad, Abbas ; Pétrot, Frédéric
Author_Institution :
TIMA Lab., Grenoble, France
Abstract :
This paper addresses link-buffer capacity allocation in the design process of best-effort 3DNoCs holding hotspot memory ports. We show that in 3DSoCs with integrated wide I/O DRAMs, the congestion spreading is different from SoCs with external DRAMs: the bottlenecks are not anymore the external memory ports but the network links that become saturated and retro-propagate the congestion. The distribution of bottleneck links is directly affected by the traffic directed to the hot memory ports. Using an analytical performance evaluation method, we determine network link buffer capacities according to the given workload composed of regular and hotspot traffics.
Keywords :
DRAM chips; integrated circuit design; network-on-chip; shared memory systems; 3DNoC; analytical performance evaluation method; congestion spreading; cost-efficient buffer sizing; design process; external DRAM; hotspot memory port; hotspot traffic; integrated wide I/O DRAM; link-buffer capacity allocation; network link buffer capacity; shared-memory 3D-MPSoC; wide I/O interface; Bandwidth; Network topology; Random access memory; Resource management; Routing; System-on-a-chip; Topology; Multiprocessor Systems-on-Chip (MPSoCs); Networks-on-Chip (NoCs); Performance Analysis;
Conference_Titel :
Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4503-1199-1
