DocumentCode :
565169
Title :
Future cache design using STT MRAMs for improved energy efficiency: Devices, circuits and architecture
Author :
Park, Sang Phill ; Gupta, Sumeet ; Mojumder, Niladri ; Raghunathan, Anand ; Roy, Kaushik
Author_Institution :
Purdue Univ., West Lafayette, IN, USA
fYear :
2012
fDate :
3-7 June 2012
Firstpage :
492
Lastpage :
497
Abstract :
Spin-transfer torque magnetic RAM (STT MRAM) has emerged as a promising candidate for on-chip memory in future computing platforms. We present a cross-layer (device-circuit-architecture) approach to energy-efficient cache design using STT MRAM. At the device and circuit levels, we consider different genres of MTJs and bitcells, and evaluate their impact on the area, energy and performance of caches. In addition, we propose microarchitectural techniques viz. sequential cache read and partial cache line update, which exploit the non-volatility of STT MRAM to further improve energy efficiency of STT MRAM caches. A detailed comparison of STT MRAM caches with SRAM-based caches is also presented. Our results indicate that the proposed optimizations significantly enhance the efficiency of STT MRAM for designing lower level caches.
Keywords :
MRAM devices; SRAM chips; cache storage; energy conservation; integrated circuit design; MTJ; STT MRAM caches; bitcells; cache area; cache energy; cache performance; cross-layer approach; device-circuit-architecture approach; energy-efficient cache design; future computing platforms; microarchitectural techniques; on-chip memory; partial cache line update; sequential cache read; spin-transfer torque magnetic RAM; Arrays; Energy consumption; Magnetic tunneling; Random access memory; Switches; System-on-a-chip; Transistors; Cache; Emerging devices; Memory; STT MRAM; Spin;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE
Conference_Location :
San Francisco, CA
ISSN :
0738-100X
Print_ISBN :
978-1-4503-1199-1
Type :
conf
Filename :
6241551
Link To Document :
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