• DocumentCode
    565178
  • Title

    Non-uniform multilevel analog routing with matching constraints

  • Author

    Ou, Hung-Chih ; Chien, Hsing-Chih Chang ; Chang, Yao-Wen

  • Author_Institution
    Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan
  • fYear
    2012
  • fDate
    3-7 June 2012
  • Firstpage
    549
  • Lastpage
    554
  • Abstract
    Symmetry, topology-matching, and length-matching constraints are three major routing considerations to improve the performance of an analog circuit. Symmetry constraints are specified to route matched nets symmetrically with respect to some common axes. Topology-matching constraints are commonly imposed on critical yet asymmetry nets with the same number of bends, vias, and wirelength. Length-matching constraints are specified to route the nets which have limited resources with the same wirelength. These three constraints can reduce current mismatches and unwanted electrical effects between two critical nets. In this paper, we propose the first work to simultaneously consider the three constraints for analog routing while minimizing total wirelength, bend numbers, via counts, and coupling noise at the same time. We first present an integer linear programming (ILP) formulation to simultaneously consider the three constraints for analog routing, and employ effective reduction techniques to further reduce the numbers of ILP variables and constraints. Then, a non-uniform multilevel routing framework is presented to enhance the performance of our routing algorithm. Experimental results show that our approach can obtain better routing results and satisfy all specified routing constraints while optimizing circuit performance.
  • Keywords
    analogue circuits; integer programming; linear programming; network routing; network topology; ILP formulation; analog circuit; bend number; coupling noise; integer linear programming; length-matching constraint; nonuniform multilevel analog routing; reduction technique; symmetry constraint; topology-matching constraint; via counts; wirelength; Algorithm design and analysis; Analog circuits; Circuit optimization; Couplings; Noise; Routing; Wires; Analog ICs; Physical Design; Routing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE
  • Conference_Location
    San Francisco, CA
  • ISSN
    0738-100X
  • Print_ISBN
    978-1-4503-1199-1
  • Type

    conf

  • Filename
    6241560